MPC5673K datasheet(102/140 Pages) FREESCALE

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MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

102

3.20

RESET characteristics

3.20.1

RESET pin characteristics

3.21

Reset sequence

This section shows the duration for different reset sequences. It describes the different reset sequences and

it specifies the start conditions and the end indication for the reset sequences depending on internal or

external VREG mode.

DRAM DQ

1.4/1.4

2.4/2.4

0.6/1.0

2.7/2.6

000

1.7/1.7

2.8/2.7

0.2/0.4

0.5/0.6

1.4/1.5

2.4/2.5

1.1/1.1

3.0/2.7

001

1.7/1.7

2.8/2.8

0.4/0.4

0.7/0.7

1.4/1.5

2.4/2.4

1.0/1.1

2.9/2.7

010

1.7/1.7

2.8/2.7

0.3/0.4

0.6/0.7

1.4/1.5

2.5/2.5

1.5/1.1

3.1/2.6

110

1.7/1.8

2.8/2.8

0.4/0.4

0.7/0.6

DRAM CLK

1.4/1.4

2.4/2.4

0.4/0.6

2.7/2.7

000

1.6/1.6

2.7/2.7

0.7/0.9

1.8/3.4

1.4/1.4

2.4/2.4

1.1/1.1

3.0/2.8

001

1.7/1.7

2.7/2.7

0.3/0.4

1.0/1.1

1.4/1.4

2.4/2.4

0.9/1.1

3.0/2.8

010

1.6/1.6

2.7/2.7

0.3/0.4

0.9/1.0

1.4/1.4

2.5/2.5

1.5/1.2

3.2/2.6

110

1.7/1.7

2.7/2.7

0.4/0.4

1.1/1.2

NOTES:

 H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay.

Table 57. RESET pin characteristics

No.

Symbol

Parameter

Conditions

Min

Max

Unit

1WFRST

SR RESET pulse is sure to be filtered

——

2WNFRST

SR RESET pulse is sure not to be filtered

—

400

—

Table 56. DRAM pads AC electrical specifications (VDD_HV_DRAM (continued) = 1.8 V)

No.

Pad Name

Prop. Delay (ns)

 H/H  L1

Rise/Fall Edge

(ns)

Drive Load

(pF)

Drive/Slew

Rate Select

Min

Max

Min

Max

MSB, LSB

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