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MPC5673K Scheda tecnica(PDF) 125 Page - Freescale Semiconductor, Inc |
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MPC5673K Scheda tecnica(HTML) 125 Page - Freescale Semiconductor, Inc |
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125 / 140 page ![]() Electrical characteristics MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor 125 3.22.8.3 MII async inputs signal timing (CRS and COL) Figure 53. MII async inputs timing diagram 3.22.8.4 MII serial management channel timing (MDIO and MDC) The FEC functions correctly with a maximum MDC frequency of 5 MHz. Table 71. MII async inputs signal timing1 NOTES: 1 Output pads configured with SRC = 0b11. No. Parameter Min Max Unit 9 CRS, COL minimum pulse width 1.5 — TX_CLK period Table 72. MII serial management channel timing1 NOTES: 1 Output pads configured with SRC = 0b11. No. Parameter Min Max Unit 10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0— ns 11 MDC falling edge to MDIO output valid (max prop delay) —25 ns 12 MDIO (input) to MDC rising edge setup 10 — ns 13 MDIO (input) to MDC rising edge hold 0— ns 14 MDC pulse width high 40% 60% MDC period 15 MDC pulse width low 40% 60% MDC period CRS, COL 9 |
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