SPEAR1340 datasheet(169/200 Pages) STMICROELECTRONICS

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SPEAr1340

Timing characteristics

Doc ID 023063 Rev 4

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THCLK is the clock period of the HCLK internal clock. The frequency is programmable, for

details refer to the RCG section of RM0078, Reference manual, SPEAr1340 architecture

and functionality.

For the I2C working as SLAVE, the only significant parameters are TSU-DAT and THD-DAT.

Table 79.

Timing characteristics for I2C in High-Speed mode

Parameter

Min(1)

HS_SCL_HCNT = 10, HS_SCL_LCNT = 33, FS_SCL_HCNT = 183, FS_SCL_LCNT = 233,

IC_SDA_HOLD=1

TSU-STA

(HS_SCL_HCNT+7)*THCLK

THD-STA

(HS_SCL_LCNT+2)*THCLK

TSU-DAT

TSCLLow - THD-DATmax

THD-DAT

(IC_SDA_HOLD)* THCLK

TSU-STO

(FS_SCL_HCNT+7)*THCLK

THD-STO

685*THCLK

Table 80.

Time characteristics for I2C in Fast-Speed mode

Parameter

Min(1)

SCL_HCNT = 183, SCL_LCNT = 233 IC_SDA_HOLD=1

TSU-STA

(SCL_HCNT+7)*THCLK

THD-STA

(SCL_HCNT+3)*THCLK

TSU-DAT

TSCLLow - THD-DATmax

THD-DAT

(IC_SDA_HOLD)* THCLK

TSU-STO

(SCL_HCNT+7)*THCLK

THD-STO

685*THCLK

Table 81.

Timing characteristics for I2C in Standard-Speed mode

Parameter

Min(1)

SCL_HCNT = 664, SCL_LCNT = 780 IC_SDA_HOLD=1

TSU-STA

(SCL_LCNT+7)*THCLK

THD-STA

(SCL_HCNT+3)*THCLK

TSU-DAT

TSCLLow - THD-DATmax

THD-DAT

(IC_SDA_HOLD)* THCLK

TSU-STO

(SCL_HCNT+7)*THCLK

THD-STO

685*THCLK

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