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OPTION_REG Scheda tecnica(PDF) 143 Page - Microchip Technology

Il numero della parte OPTION_REG
Spiegazioni elettronici  Digitally Enhanced Power Analog Controller with Integrated Synchronous Driver
PDF  222 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

OPTION_REG Scheda tecnica(HTML) 143 Page - Microchip Technology

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 2013 Microchip Technology Inc.
DS22331A-page 143
MCP19111
26.1.4
PWM DUTY CYCLE (DCLOCK)
The PWM duty cycle (DCLOCK) is specified by writing
to the PWMRL register. Up to 8-bit resolution is
available. The following equation is used to calculate
the PWM duty cycle (DCLOCK):
EQUATION 26-4:
The PWMRL bits can be written to at any time, but the
duty cycle value is not latched into PWMRH until after
a match between PR2 and TMR2 occurs.
26.2
Operation during Sleep
When the device is placed in Sleep, the allocated
timer will not increment and the state of the module will
not change. If the CLKPIN pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
PWM DUTY CYCLE=PWMRL x TOSC x(T2 PRESCALE VALUE)
TABLE 26-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PWM MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON
—
—
—
—
—
—
—
CLKSEL
110
T2CON
—
—
—
—
—
TMR2ON T2CKPS1 T2CKPS0
139
PR2
Timer2 Module Period Register
138*
PWMRL
PWM Register Low Byte
141*
PWMPHL
SLAVE Phase Shift Byte
141*
BUFFCON
MLTPH2
MLTPH1
MLTPH0
ASEL4
ASEL3
ASEL2
ASEL1
ASEL0
56
Legend:
— = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.
*
Page provides register information.



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