STM32F415VG datasheet(143/186 Pages) STMICROELECTRONICS

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STM32F415xx, STM32F417xx

Electrical characteristics

Synchronous waveforms and timings

Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through

Table 82 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

•

BurstAccessMode = FSMC_BurstAccessMode_Enable;

•

MemoryType = FSMC_MemoryType_CRAM;

•

WriteBurst = FSMC_WriteBurst_Enable;

•

CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)

•

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the THCLK is the HCLK clock period (with maximum

FSMC_CLK = 60 MHz).

th(NE_NWE)

FSMC_NWE high to FSMC_NE high hold time

THCLK

-ns

tv(A_NE)

FSMC_NEx low to FSMC_A valid

tv(NADV_NE)

FSMC_NEx low to FSMC_NADV low

tw(NADV)

FSMC_NADV low time

THCLK– 2

THCLK+ 1

th(AD_NADV)

FSMC_AD(address) valid hold time after

FSMC_NADV high)

THCLK–2

th(A_NWE)

Address hold time after FSMC_NWE high

THCLK

-ns

th(BL_NWE)

FSMC_BL hold time after FSMC_NWE high

THCLK–2

tv(BL_NE)

FSMC_NEx low to FSMC_BL valid

1.5

tv(Data_NADV) FSMC_NADV high to Data valid

THCLK–0.5

th(Data_NWE)

Data hold time after FSMC_NWE high

THCLK

-ns

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

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