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PIC16F1946 Scheda tecnica(PDF) 217 Page - Microchip Technology |
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PIC16F1946 Scheda tecnica(HTML) 217 Page - Microchip Technology |
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217 / 478 page  2010-2012 Microchip Technology Inc. DS41414D-page 217 PIC16(L)F1946/47 23.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 23.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 238 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 216* CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 216* INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 93 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE 94 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 95 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 97 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF C3IF CCP2IF 98 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 99 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON 207 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 208 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 203* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 203* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 131 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 134 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 140 TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 143 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. Note 1: Applies to ECCP modules only. * Page provides register information. |
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