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dsPIC33FJ64GS406 Scheda tecnica(PDF) 121 Page - Microchip Technology |
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dsPIC33FJ64GS406 Scheda tecnica(HTML) 121 Page - Microchip Technology |
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121 / 456 page ![]() 2009-2012 Microchip Technology Inc. DS70591E-page 121 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.9 Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Table 6-2 provides a summary of the Reset flag bit operation. TABLE 6-2: RESET FLAG BIT OPERATION Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR, BOR IOPWR (RCON<14>) Illegal opcode or uninitialized W register access or Security Reset POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. |
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