M68ICS08GR datasheet(260/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Technical Data

MC68HC908GR8 — Rev 4.0

260

Serial Communications Interface (SCI)

MOTOROLA

PEIE — Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI receiver CPU interrupt requests

generated by the parity error bit, PE. See SCI Status Register 1.

Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabled

18.9.4 SCI Status Register 1

SCI status register 1 (SCS1) contains flags to signal these conditions:

•

Transfer of SCDR data to transmit shift register complete

•

Transmission complete

•

Transfer of receive shift register data to SCDR complete

•

Receiver input idle

•

Receiver overrun

•

Noisy data

•

Framing error

•

Parity error

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a

character to the transmit shift register. SCTE can generate an SCI

transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,

SCTE generates an SCI transmitter CPU interrupt request. In normal

Address:

$0016

Bit 7

Bit 0

Read:

SCTE

SCRF

IDLE

Write:

Reset:

11000000

= Unimplemented

Figure 18-12. SCI Status Register 1 (SCS1)

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