M68ICS08GR datasheet(294/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

294

System Integration Module (SIM)

MOTOROLA

19.8.1 SIM Break Status Register

The SIM break status register (SBSR) contains a flag to indicate that a

break caused an exit from stop mode or wait mode.

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop

mode after exiting from a break interrupt. Clear SBSW by writing a

logic 0 to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt.

0 = Stop mode or wait mode was not exited by break interrupt.

SBSW can be read within the break state SWI routine. The user can

modify the return address on the stack by subtracting one from it. The

following code is an example of this. Writing 0 to the SBSW bit clears it.

Address:

$FE00

Bit 7

654321

Bit 0

Read:

RRRRRR

SBSW

Write:

Note(1)

Reset:

00000000

R= Reserved

Note: 1. Writing a logic 0 clears SBSW.

Figure 19-20. SIM Break Status Register (SBSR)

This code works if the H register has been pushed onto the stack in the break

service routine software. This code should be executed at the end of the break

service routine software.

HIBYTE

EQU

;

LOBYTE

EQU

;

If not SBSW, do RTI

;

BRCLR

SBSW,SBSR, RETURN

;

See if wait mode or stop mode was exited by

break.

TST

LOBYTE,SP

;If RETURNLO is not zero,

BNE

DOLO

;then just decrement low byte.

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