ISL80102, ISL80103

3

FN6660.6

June 14, 2013

Pin Configuration

ISL80102, ISL80103

(10 LD 3x3 DFN)

TOP VIEW

2

3

4

1

5

9

8

7

10

6

SENSE/ADJ

PG

GND

DNC

ENABLE

SS

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

1, 2

VOUT

Output voltage pin.

3

SENSE/ADJ

Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT.

4

PG

VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used.

5GND

GND pin.

6

SS

External cap adjusts in-rush current.

7

ENABLE

VIN independent chip enable. TTL and CMOS compatible.

8

DNC

Do not connect this pin to ground or supply. Leave floating.

9, 10

VIN

Input supply pin.

EPAD

EPAD must be connected to copper plane with as many vias as possible for proper electrical and optimal thermal

performance.

Typical Application

FIGURE 2. TYPICAL APPLICATION DIAGRAM

ISL80102, ISL80103

9

10

ENABLE

7

SS

6

GND

2.5V ±10%

10µF

5

PG

4

1

2

1.8V

10µF

100kΩ

ADJ

3

PGOOD

10kΩ

1.0kΩ

1500pF

EN

OPEN DRAIN COMPATIBLE

*CSS is optional, (see Note 11) on page 5.

2.61kΩ