RM0352 datasheet(106/138 Pages) STMICROELECTRONICS

106 / 138 page

SPI (serial peripheral interface)

RM0352

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DocID024647 Rev 1

Table 100 shows the bit assignments.

11.4.5

Clock prescale register, SSPCPSR

The SSPCPSR register characteristics are:

Purpose

The SSPCPSR is the clock prescale register and specifies the

division factor by which the input SSPCLK must be internally divided

before further use.

The value programmed into this register must be an even number

between 2 - 254. The least significant bit of the programmed number

is hard-coded to zero. If an odd number is written to this register,

data read back from this register has the least significant bit as zero.

Usage constraints

There are no usage constraints.

Configurations

Available in all SSP configurations.

Attributes

See

Table 96 on page 101.

Table 100. SSPSR register bit assignments

Bits

Name

Function

[15:5]

RESERVED, read unpredictable, should be written as 0.

[4]

BSY

PrimeCell SSP busy flag, RO:

SSP is idle.

SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.

[3]

RFF

Receive FIFO full, RO:

receive FIFO is not full.

receive FIFO is full.

[2]

RNE

Receive FIFO not empty, RO:

receive FIFO is empty.

receive FIFO is not empty.

[1]

TNF

Transmit FIFO not full, RO:

transmit FIFO is full.

transmit FIFO is not full.

[0]

TFE

Transmit FIFO empty, RO:

transmit FIFO is not empty.

transmit FIFO is empty.

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