STM32F479II datasheet(144/208 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F479xx

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DocID028010 Rev 2

SAI characteristics

Unless otherwise specified, the parameters given in Table 66 for SAI are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C=30 pF

•

Measurement points are performed at CMOS levels: 0.5 VDD

Refer to Section 5.3.20 for more details on the input/output alternate

function

characteristics (SCK,SD,WS).

Table 66. SAI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCKL

SAI Main clock output

256 x 8K

256xFs

MHz

fCK

SAI clock frequency(2)

Master data: 32 bits

128xFs(3)

Slave data: 32 bits

128xFs

tv(FS)

FS valid time

Master mode,

2.7V ≤ VDD ≤ 3.6V

-17

Master mode,

1.71V ≤ VDD ≤ 3.6V

-23

tsu(FS)

FS setup time

Slave mode

th(FS)

FS hold time

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

th(SD_B_ST)

Data output valid time

Slave transmitter (after enable edge),

2.7V ≤ VDD ≤ 3.6V

-14

Slave transmitter (after enable edge),

1.71V ≤ VDD ≤ 3.6V

-23

th(SD_B_ST)

Data output hold time

Slave transmitter (after enable edge)

tv(SD_A_MT)

Data output valid time

Master transmitter (after enable edge),

2.7V ≤ VDD ≤ 3.6V

-20

Master transmitter (after enable edge),

1.71V ≤ VDD ≤ 3.6V

-26

th(SD_A_MT)

Data output hold time

Master transmitter (after enable edge)

1. Guaranteed based on test during characterization.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With Fs = 192 kHz.

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