WM8993 datasheet(126/229 Pages) WOLFSON

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WM8993

Production Data

PD, November 2010, Rev 4.0

126

ADC / DAC CLOCK CONTROL

The clocking of the ADC and DAC circuits is derived from CLK_DSP. This signal is generated from

CLK_SYS and is separately enabled, using the register bit CLK_SYS_ENA.

The ADC and DAC sample rates are independently selectable, relative to CLK_DSP. The

programmable dividers allow selection of the commonly used sample rates from typical audio system

clocking frequencies (eg. 12.288MHz). In Manual Clocking Configuration mode, these are controlled

using the register bits described in Table 82. In Automatic Clocking Configuration mode, the ADC

and DAC clocking dividers are configured automatically by the WM8993.

The ADC_DIV register controls the ADC clocking rate. The ADC_DIV register should be set to derive

256 x fs from CLK_DSP, where fs is the ADC sampling rate (eg. 48kHz).

Two modes of ADC operation can be selected using the ADC_OSR128 bit; in 48kHz sample mode,

setting the ADC_OSR128 bit results in 128x oversampling. This bit is enabled by default, giving best

audio performance. Deselecting this bit gives 64x oversampling in 48kHz mode, resulting in

decreased power consumption.

The DAC_DIV and the DAC_DIV4 registers control the DAC clocking rate. For normal operation,

DAC_DIV4 is set, and the DAC_DIV register should be set to derive 256 x fs from CLK_DSP, where

fs is the DAC sampling rate.

Higher performance DAC operation can be achieved by increasing the DAC oversample rate. This is

available in Automatic Clocking Configuration mode only - see Table 81.

The ADC / DAC Clock Control registers are defined in Table 82.

In Manual Clocking Configuration mode, all of these registers may be controlled.

In Automatic Clocking Configuration mode, the CLK_SYS_ENA field must be set by the user. The

ADC_OSR128 bit may be selected if required. The remaining ADC / DAC Clock Control registers are

ignored and invalid in Automatic mode.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Clocking 2

7:5

ADC_DIV [2:0]

000

ADC Sample Rate Divider

000 = CLK_SYS / 1

001 = CLK_SYS / 1.5

010 = CLK_SYS / 2

011 = CLK_SYS / 3

100 = CLK_SYS / 4

101 = CLK_SYS / 5.5

110 = CLK_SYS / 6

111= Reserved

Note - this field is ignored and invalid in

Automatic Clocking Configuration mode.

4:2

DAC_DIV [2:0]

000

DAC Sample Rate Divider

000 = CLK_SYS / 1

001 = CLK_SYS / 1.5

010 = CLK_SYS / 2

011 = CLK_SYS / 3

100 = CLK_SYS / 4

101 = CLK_SYS / 5.5

110 = CLK_SYS / 6

111= Reserved

Note - this field is ignored and invalid in

Automatic Clocking Configuration mode.

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