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WM8993 Scheda tecnica(PDF) 138 Page - Wolfson Microelectronics plc |
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WM8993 Scheda tecnica(HTML) 138 Page - Wolfson Microelectronics plc |
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138 / 229 page ![]() WM8993 Production Data w PD, November 2010, Rev 4.0 138 The sequence of signals associated with a single register write operation is illustrated in Figure 61. Figure 61 Control Interface Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 62. Figure 62 Control Interface Register Read The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 92. Note that multiple write and multiple read operations are supported using the auto-increment mode. This feature enables the host processor to access sequential blocks of the data in the WM8993 register map faster than is possible with single register operations. TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge (SDAT Low) A ¯ ¯ Not Acknowledge (SDAT High) P Stop Condition R/W ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to WM8993 [Grey field] Data flow from WM8993 to bus master Table 92 Control Interface Terminology |
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