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PC87365 Scheda tecnica(PDF) 159 Page - National Semiconductor (TI) |
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PC87365 Scheda tecnica(HTML) 159 Page - National Semiconductor (TI) |
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159 / 215 page ![]() 9.0 Voltage Level Monitor (VLM) (Continued) 159 www.national.com 9.5.5 Voltage Event to SMI Register 1 (VEVSMI1) This register is one of two registers that controls event routing to SMI. Location: Offset 03h Type: R/W Bit 76543210 Name Reserved AVDD Event to SMI Enable VBAT Event to SMI Enable VDD Event to SMI Enable Reset 00000000 Bit Description 7-3 Reserved. 2 AVDD Event to SMI Enable. 0: Disabled (default) 1: Enabled 1 VBAT Event to SMI Enable. 0: Disabled (default) 1: Enabled 0 VDD Event to SMI Enable. 0: Disabled (default) 1: Enabled |
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