PC87365 datasheet(173/215 Pages) NSC

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10.0 Temperature Sensor (TMS) (Continued)

173

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10.3 TMS REGISTERS

The TMS registers are divided into two groups: TMS Control and Status registers and TMS channel registers. The TMS

channel registers are duplicated for each channel.

The register maps in this chapter use the following abbreviations for Type:

• R/W = Read/Write.

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W = Write.

• RO = Read Only.

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

10.3.1

TMS Register Map

Table 52. TMS Control and Status Register Map

Table 53. TMS Channel Register Map (One per Channel)

Offset

Mnemonic

Type

Section

00h

TEVSTS

Temperature Event Status

10.3.2

01h

Reserved

02h

TEVSMI

Temperature Event to SMI

R/W

10.3.3

03h

Reserved

04h

TEVIRQ

Temperature Event to IRQ

R/W

10.3.4

05h-

07h

Reserved

08h

TMSCFG

TMS Conﬁguration

R/W

10.3.5

09h

TMSBS

TMS Bank Select

R/W

10.3.6

Offset

Mnemonic

Type

Section

0Ah

TCHCFST

Temperature Channel Configuration and Status

Varies per bit

10.3.7

0Bh

RDCHT

Read Channel Temperature

10.3.8

0Ch

CHTH

Channel Temperature High Limit

R/W

10.3.9

0Dh

CHTL

Channel Temperature Low Limit

R/W

10.3.10

0Eh

CHOTL

Channel Overtemperature Limit

R/W

10.3.11

0Fh

Reserved

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