MT9072AB datasheet(205/275 Pages) ZARLINK

205 / 275 page

MT9072

Data Sheet

205

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-9

not used.

8GAIM

(0)

GAIM When unmasked an interrupt is generated when go-ahead pattern (01111111)

was detected by the HDLC receiver.

7EOPDIM

(0)

End of Packet Data Interrupt Mask.When unmasked an interrupt is initiated when an

end of packet (EOP) byte was written into the RX FIFO by the HDLC receiver.

TEOPIM

(0)

Transmit End of Packet Interrupt Mask.When unmasked an interrupt is initiated

when the byte about to be read from the RX FIFO is the last byte of the packet. An

interrupt is also initiated if the Rx FIFO is read and there is no data in it.

5EOPRIM

(0)

End of Packet Received Interrupt Mask.When unmasked an interrupt is initiated

when the byte about to be read from the RX FIFO is the last byte of the packet. An

interrupt is also initiated if the Rx FIFO is read and there is no data in it.

4TXFLIM

(0)

Transmit Fifo Low Interrupt Mask.When unmasked an interrupt is initiated when the

Tx FIFO is emptied below the selected low threshold level.

3FAIM

(0)

Transmit Elastic Buffer full interrupt Mask. When unmasked an interrupt is initiated

whenever the transmit elastic buffer is full.If 1 - masked, 0 - unmasked.

TXUNDERIM

(0)

Transmit Fifo Underrun Interrupt Mask. interrupt is initiated for TX FIFO underrun

indication.

RXFFIM

(0)

Receive Fifo full Threshold interrupt Mask. When unmasked an interrupt is initiated

whenever the Rx FIFO is filled above the selected full threshold level.

RXOVFLIM

(0)

Receive Fifo Overflow Interrupt Mask. When unmasked an interrupt is initiated

whenever the 16 byte RX FIFO overflowed (i.e. an attempt to write to a 16 byte full RX

FIFO).

Table 181 - HDLC Interrupt Mask Register (Address Y43) (E1)

Bit

Name

Functional Description

not used.

RCRCRM

(0)

Remote CRC-4 and RAI Mask. This is the mask bit for the RCRCRI interrupt status bit in the

Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address

Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

RSLPM

(0)

Receive Slip Mask. This is the mask bit for the RSLPI interrupt status bit in the Sync (Sync,

CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If this

mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero, the

corresponding interrupt bit will function normally.

(0)

Receive Y-bit Mask. This is the mask bit for the YI interrupt status bit in the Sync (Sync,

CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If this

mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero, the

corresponding interrupt bit will function normally.

Table 182 - Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address Y44)

(E1)

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