MT9072AB datasheet(219/275 Pages) ZARLINK

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MT9072

Data Sheet

219

Zarlink Semiconductor Inc.

2F0EM

(0)

Framer 0 Elastic Mask. This is the mask bit for the F0EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

1F0RM

(0)

Framer 0 Rx Line Mask. This is the mask bit for the F0RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

0F0SM

(0)

Framer 0 Sync and Overflow Mask. This is the mask bit for the F0SVS status bit in the Interrupt

Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

Bit

Name

Functional Description

F7HM

(0)

Framer 7 HDLC Mask. This is the mask bit for the F7HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F7EM

(0)

Framer 7 Elastic Mask. This is the mask bit for the F7EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F7RM

(0)

Framer 7 Rx Line Mask. This is the mask bit for the F7RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F7SM

(0)

Framer 7 Sync and Overflow Mask. This is the mask bit for the F7SVS status bit in the Interrupt

Vector Register(address 911). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F6HM Framer 6 HDLC Mask. This is the mask bit for the F6HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F6EM

(0)

Framer 6 Elastic Mask. This is the mask bit for the F6EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

Table 197 - Interrupt Vector 2 Mask Register (R/W Address 903) (E1)

Bit

Name

Functional Description

Table 196 - Interrupt Vector 1 Mask Register (R/W Address 902) (E1)

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