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STM32F479AI Scheda tecnica(PDF) 126 Page - STMicroelectronics |
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STM32F479AI Scheda tecnica(HTML) 126 Page - STMicroelectronics |
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126 / 217 page ![]() Electrical characteristics STM32F479xx 126/217 DocID028010 Rev 3 Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram 5.3.14 MIPI D-PHY PLL characteristics The parameters given in Table 47 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17. Table 47. DSI-PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 4 - 100 MHz fPLL_INFIN PFD input clock - 4 - 25 fPLL_OUT PLL multiplier output clock - 31.25 - 500 fVCO_OUT PLL VCO output - 500 - 1000 tLOCK PLL lock time - - - 200 µs |
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