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OMAP3530ECUS Scheda tecnica(PDF) 231 Page - Texas Instruments

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Il numero della parte OMAP3530ECUS
Spiegazioni elettronici  Applications Processors
PDF  265 Pages
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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OMAP3530ECUS Scheda tecnica(HTML) 231 Page - Texas Instruments

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HDQ
tHW 1
tHW 0
tCYCH
030-096
HDQ
tB
tBR
030-095
OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 6-109. Correspondence Standard vs. TI Timing References (continued)
TI-OMAP
STANDARD-I2C
S/F Mode
HS Mode
I7
th(SCLH-RSTART)
TSU;STO
TSU;STO
I8
tw(SDAH)
TBUF
6.6.6
HDQ / 1-Wire Interfaces
This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single
wire to communicate between the master and the slave. The protocols employ an asynchronous return to
1 mechanism where, after any command, the line is pulled high.
6.6.6.1
HDQ Protocol
Table 6-110 and Table 6-111 assume testing over the recommended operating conditions (see Figure 6-
55 through Figure 6-58).
Table 6-110. HDQ Timing Requirements
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tCYCD
Bit window
253
μs
tHW1
Reads 1
68
tHW0
Reads 0
180
tRSPS
Command to host respond time(1)
(1)
Defined by software.
Table 6-111. HDQ Switching Characteristics
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
tB
Break timing
193
μs
tBR
Break recovery
63
tCYCH
Bit window
253
tDW1
Sends1 (write)
1.3
tDW0
Sends0 (write)
101
Figure 6-55. HDQ Break (Reset) Timing
Figure 6-56. HDQ Read Bit Timing (Data)
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
231
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Product Folder Links: OMAP3530 OMAP3525



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