TNETV1644ZDU6 datasheet(230/306 Pages) TI1

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PCLK

(Positive Edge Clocking)

13, 31

PCLK

(Negative Edge Clocking)

11, 29

VCTL(A)

A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE

B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]

VDATA(B)

14, 32

12, 30

VPBECLK

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 6-44. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to PCLK and VPBECLK(1) (see Figure 6-25)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

PARAMETER

UNIT

MIN

MAX

td(PCLK-VCTLV)

Delay time, PCLK edge to VCTL valid

td(PCLK-VCTLIV)

Delay time, PCLK edge to VCTL invalid

2.5

td(PCLK-VDATAV)

Delay time, PCLK edge to VDATA valid

td(PCLK-VDATAIV)

Delay time, PCLK edge to VDATA invalid

2.5

td(VPBECLK-VCTLV)

Delay time, VPBECLK rising edge to VCTL valid

td(VPBECLK-VCTLIV)

Delay time, VPBECLK rising edge to VCTL invalid

2.5

td(VPBECLK-VDATAV)

Delay time, VPBECLK rising edge to VDATA valid

td(VPBECLK-VDATAIV)

Delay time, VPBECLK rising edge to VDATA invalid

2.5

(1)

PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising

edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.

Figure 6-25. VPBE Output Timing With Respect to PCLK and VPBECLK

230

Peripheral Information and Electrical Specifications

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