ST72345C4 datasheet(241/247 Pages) STMICROELECTRONICS

241 / 247 page

ST72344xx, ST2345xx

Known limitations

Doc ID 12321 Rev 6

241/247

OUT: RIM

JP while_loop

.call_routine; entry to call_routine

PUSH A

PUSH X

PUSH CC

.ext1_rt; entry to interrupt routine

LD A,#$00

LD sema,A

IRET

16.1.2

Unexpected reset fetch

If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt

controller does not recognise the source of the interrupt and, by default, passes the reset

vector address to the CPU.

Workaround

To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.

16.2

Clearing active interrupts outside interrupt routine

When an active interrupt request occurs at the same time as the related flag is being

cleared, an unwanted reset may occur.

Note:

Clearing the related interrupt mask will not generate an unwanted reset.

Concurrent interrupt context

The symptom does not occur when the interrupts are handled normally, i.e. when:

●

The interrupt flag is cleared within its own interrupt routine

●

The interrupt flag is cleared within any interrupt routine

●

The interrupt flag is cleared in any part of the code while this interrupt is disabled

If these conditions are not met, the symptom can be avoided by implementing the following

sequence:

Perform SIM and RIM operation before and after resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts are handled normally, i.e. when:

●

The interrupt flag is cleared within its own interrupt routine

●

The interrupt flag is cleared within any interrupt routine with higher or identical priority

level

●

The interrupt flag is cleared in any part of the code while this interrupt is disabled

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