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WM8232 Scheda tecnica(PDF) 141 Page - Cirrus Logic |
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WM8232 Scheda tecnica(HTML) 141 Page - Cirrus Logic |
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141 / 141 page ![]() WM8232 Rev 4.6 141 DATE REV ORIGINATOR CHANGES PAGE 22/05/14 4.2 AA Added data latency specification Updated tPER, tMCLKH and tMCLKL description Corrected test condition for LVDS output data timing Added description of LVDS synchronous output Removed tPER and tMCLKD description Removed tTRGD and tPCKD description Updated Data trigger timing delay specification Corrected Trigger data, Channel ID description Corrected TG MASK TIMING description Added description for Data Output Configuration Corrected register description of LVDS ORDER(R07h[3]) Corrected register description of SEL_PCK7,8,9,10,11 15 15 17 31 33,36 36 37 38 42 59,60 68 94,95 19/08/14 4.3 AA Corrected pin name (PO0~PO9) 5,61,71~73 20/10/15 4.4 PH Test limit (min/max) conditions added in Elec Chars Signal timing limits added Amendment to LVDS_AMP description 8-10 15, 36 60, 69 27/11/15 4.5 PH Electrical characteristics updated 8-10 25/03/16 4.6 PH Digital pin output impedance updated 10 |
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