General description
The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with up to 128 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical
performance in interrupt service routines and DSP algorithms, this increases performance
up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
The LPC2361/2362 are ideal for multi-purpose serial communication applications. They
incorporate a 10/100 Ethernet Media Access Controller (MAC) (LPC2362 only), USB full
speed device with 4 kB of endpoint RAM, four UARTs, two CAN channels, an SPI
interface, two Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface.
This blend of serial communications interfaces combined with an on-chip 4 MHz internal
oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet (available as general purpose
SRAM for the LPC2361), 8 kB SRAM for USB and general purpose use, together with
2 kB battery powered SRAM make these devices very well suited for communication
gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit
DAC, one PWM unit, a CAN control unit, and up to 70 fast GPIO lines with up to 12 edge
or level sensitive external interrupt pins make these microcontrollers particularly suitable
for industrial control and medical systems.

Features and benefits
 ARM7TDMI-S processor, running at up to 72 MHz.
 Up to 128 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
 8 kB (LPC2361) or 32 kB (LPC2362) of SRAM on the ARM local bus for high
performance CPU access.
 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
 8 kB SRAM for general purpose DMA use; also accessible by the USB.
 Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA (LPC2362 only), USB DMA, and program execution from on-chip flash
with no contention between those functions. A bus bridge allows the Ethernet DMA to
access the other AHB subsystem.
 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
 General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I2S port, as well as for memory-to-memory transfers.
 Serial interfaces:
 Ethernet MAC with associated DMA controller (LPC2362 only). These functions
reside on an independent AHB.
 USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller.
 Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
 CAN controller with two channels.
 SPI controller.
 Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA
controller.
 Three I2C-bus interfaces (one with open-drain and two with standard port pins).
 I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
 Other peripherals:
 70 general purpose I/O pins with configurable pull-up/down resistors.
 10-bit ADC with input multiplexing among 6 pins.
 10-bit DAC.
 Four general purpose timers/counters with a total of 8 capture inputs and 10
compare outputs. Each timer block has an external count input.
 One PWM/timer block with support for three-phase motor control. The PWM has
two external count inputs.
 Real-Time Clock (RTC) with separate power pin, clock source can be the RTC
oscillator or the APB clock.
 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
 Standard ARM test/debug interface for compatibility with existing tools.
 Emulation trace module supports real-time trace.
 Single 3.3 V power supply (3.0 V to 3.6 V).
 Four reduced power modes: idle, sleep, power-down, and deep power-down.
 Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
 Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt).
 Two independent power domains allow fine tuning of power consumption based on
needed features.
 Each peripheral has its own clock divider for further power saving.
 Brownout detect with separate thresholds for interrupt and forced reset.
 On-chip power-on reset.
 On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.