1 Features
• 2 V to 5.5 V VCC operation
• Maximum tpd of 10.5 ns at 5 V
• Support mixed-mode voltage operation on
all ports
• Ioff supports partial-power-down mode
operation
• Latch-up performance exceeds 250 mA per
JESD 17

2 Applications
• Increase the Number of Inputs on a Microcontroller

3 Description
The SN74LV165A device is a parallel-load, 8-bit shift
registers designed for 2 V to 5.5 V VCC operation.
When the device is clocked, data is shifted toward the
serial output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs that are
enabled by a low level at the shift/load (SH/ LD) input.
The ’LV165A devices feature a clock-inhibit function
and a complemented serial output, Q H.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow
through the devices when they are powered down.