DESCRIPTION
The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

FEATURES
● Wide supply voltage range of 1.2 V to 3.6 V
● Complies with JEDEC standard no. 8-1A.
● CMOS low power consumption
● Direct interface with TTL levels
● Current drive ± 24 mA at 3.0 V
● MULTIBYTETM flow-through standard pin-out architecture
● Low inductance multiple VCC and GND pins for minimum noise
   and ground bounce
● Output drive capability 50 Ω transmission lines @ 85°C
● Input diodes to accommodate strong drivers