FEATURES
■ Access Times of 50*, 60, 70, 90, 120, 150ns
■ Packaging
   • 32 lead, Hermetic Ceramic, 0.400" SOJ (Package 101)
   • 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
   • 32 lead, Flatpack (Package 220)
   • 32 lead, Formed Flatpack (Package 221)
   • 32 pin, Rectangular Ceramic Leadless Chip
      Carrier (Package 601)
■ 100,000 Erase/Program Cycles Minimum
■ Sector Erase Architecture
   • 8 equal size sectors of 16KBytes each
   • Any combination of sectors can be concurrently
      erased. Also supports full chip erase

■ Organized as 128Kx8
■ Commercial, Industrial and Military Temperature Ranges
■ 5 Volt Programming. 5V ± 10% Supply.
■ Low Power CMOS
■ Embedded Erase and Program Algorithms
■ TTL Compatible Inputs and CMOS Outputs
■ Page Program Operation and Internal Program Control Time.