Description
• 120 MIPS at 120MHz
• 6K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines and
four chip selects
• One (1) Serial Port Interface (SPI) or one (1) Improved
Synchronous Serial Interface (ISSI)
• One (1) Serial Communication Interface (SCI)
• Interrupt Controller
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• 81-pin MAPBGA package
• Up to 11 GPIO

1.1 Features
1.1.1Core
•Efficient 16-bit engine with dual Harvard architecture
•120 Million Instructions Per Second (MIPS) at 120MHz core frequency
•Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
•Four (4) 36-bit accumulators including extension bits
•16-bit bidirectional shifter
•Parallel instruction set with unique DSP addressing modes
•Hardware DO and REP loops
•Three (3) internal address buses and one (1) external address bus
•Four (4) internal data buses and one (1) external data bus
•Instruction set supports both DSP and controller functions
•Four (4) hardware interrupt levels
•Five (5) software interrupt levels
•Controller-style addressing modes and instructions for compact code
•Efficient C Compiler and local variable support
•Software subroutine and interrupt stack with depth limited only by memory
•JTAG/Enhanced OnCE debug programming interface

1.1.2Memory
•Harvard architecture permits as many as three simultaneous accesses to program and data memory
•On-chip memory includes:
—6K × 16-bit Program SRAM
—4K × 16-bit Data SRAM
—1K × 16-bit Boot ROM
•21 External Memory Address lines, 16 data lines and four (4) programmable chip select signals

1.1.3Peripheral Circuits for DSP56852
•General Purpose 16-bit Quad Timer with two external pins*
•One (1) Serial Communication Interface (SCI)*
•One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) module*
•Interrupt Controller
•Computer Operating Properly (COP)/Watchdog Timer
•JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
•81-pin MAPBGA package
•Up to 11 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4Energy Information
•Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
•Wait and Stop modes available