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873991 Scheda tecnica (PDF) - Renesas Technology Corp

873991 Datasheet PDF - Renesas Technology Corp
Il numero della parte 873991
Scarica  873991 Scarica
Grandezza file   532.67 Kbytes
Page   19 Pages
Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp
Spiegazioni elettronici LOW VOLTAGE, LVCMOS/ LVPECL-TO-LVPECL/ECL CLOCK GENERATOR

873991 Datasheet (PDF)

Go To PDF Page Scarica Scheda tecnica
873991 Datasheet PDF - Renesas Technology Corp

Il numero della parte 873991
Scarica  873991 Click to download

Grandezza file   532.67 Kbytes
Page   19 Pages
Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp
Spiegazioni elettronici LOW VOLTAGE, LVCMOS/ LVPECL-TO-LVPECL/ECL CLOCK GENERATOR

873991 Scheda tecnica (HTML) - Renesas Technology Corp


873991 Dettagli del prodotto

GENERAL DESCRIPTION
The 873991 is a low voltage, low skew, 3.3V LVPECL
or ECL Clock Generator . The 873991 has two selectable
clock inputs. The PCLK, nPCLK pair can accept an LVPECL
input and the TEST_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with
frequency confi gurable outputs. An external feedback input and
output regenerates clocks with “zero delay”.
The four independent banks of outputs each have their
own output dividers, which allow the device to generate a
multitude of different bank frequency ratios and output-toinput frequency ratios. The output frequency range is 25MHz to
400MHz and the input frequency range is 6.25MHz to 125MHz.
The PLL_SEL input can be used to bypass the PLL for test
and system debug purposes. In bypass mode, the input clock
is routed around the PLL and into the internal output dividers.
The 873991 also has a SYNC output which can be used for
system synchronization purposes. It monitors Bank A and Bank
C outputs for coincident rising edges and signals a pulse per the
timing diagrams in this data sheet. This feature is used primarily
in applications where Bank A and Bank C are running at different
frequencies, and is particularly useful when they are running at
non-integer multiples of each other.
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.

FEATURES
• 14 differential LVPECL outputs
• Selectable differential LVPECL or TEST_CLK inputs
• PCLK, nPCLK can accept the following input levels:
LVPECL, CML, SSTL
• TEST_CLK accepts the following input levels:
LVCMOS, LVTTL
• Input frequency range: 6.25MHz to 125MHz
• Output frequency: 400MHz (maximum)
• VCO range: 200MHz to 800MHz
• Output skew: 250ps (maximum)
• Cycle-to-cyle jitter: ±50ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -3.135V
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Lead-Free package fully RoHS compliant
• Use replacement part 873996AYLF




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A proposito di Renesas Technology Corp


Renesas Technology Corp è una società di semiconduttori giapponesi che fornisce una vasta gamma di microcontrollori, sistemi su chip e dispositivi analogici e di alimentazione per varie applicazioni nei mercati automobilistici, industriali e di consumo.
La società è stata formata nel 2010 attraverso la fusione di NEC Electronics Corporation e Renesas Technology Corporation.
Renesas è uno dei più grandi fornitori di microcontrollori al mondo ed è noto per la sua esperienza nello sviluppo di tecnologie avanzate in settori come l'Internet of Things (IoT), l'intelligenza artificiale (AI) e l'elettronica automobilistica.
La società ha operazioni in oltre 20 paesi e i suoi prodotti vengono utilizzati in una vasta gamma di applicazioni.

*Queste informazioni sono solo a scopo informativo generale, non saremo responsabili per eventuali perdite o danni causati dalle informazioni di cui sopra.




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