Features/Benefits
• External feedback path; adjustable input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can
share same SMBus segment
• 7 dedicated OE# pins; hardware control of outputs
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL BW; minimizes jitter peaking in
downstream PLL's
• Spread spectrum compatible; tracks spreading input
clock for EMI reduction
• SMBus Interface; unused outputs can be disabled
• 100MHz & 133.33MHz PLL mode; legacy QPI support
• Undriven differential outputs in Power Down mode for
maximum power savings
Key Specifications
• Cycle-to-cycle jitter: <50ps
• Output-to-output skew: <65ps
• Input-to-output delay: User adjustable
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 <1ps rms
• Phase jitter: QPI 9.6GB/s <0.2ps rms