FEATURES:
• Choose among the following memory organizations:
IDT72V255LA 8,192 x 18
IDT72V265LA 16,384 x 18
• Pin-compatible with the IDT72V275/72V285 and IDT72V295/
72V2105 SuperSync FIFOs
• Functionally compatible with the 5 Volt IDT72255/72265 family
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• 5V input tolerant
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)