Features
• Generates T1, E1, OC-3 and other common telecom
clock frequencies from an 8kHz frame clock
• Configurable jitter attenuation characteristics, excellent
for use as a Stratum source de-jitter circuit
• 2:1 Input MUX for input reference clocks
• VCXO-based clock generation offers very low jitter and
phase noise generation
• Output clock is phase and frequency locked to the
selected input reference clock
• Fixed input to output phase relationship (except for 1.544
MHz and 2.048 MHz output selections)
• +115ppm minimum crystal frequency pullability range,
using recommended crystal
• Industrial temperature range
• Low power CMOS technology
• 20 pin SOIC package
• Single 3.3V power supply
• Pb (lead) free package