Features
• Nine differential 2.5V, 3.3V LVPECL/ECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• PCLK, nPCLK supports the following input types: LVPECL, LVDS,
CML, SSTL
• Output frequency: 1.6GHz (maximum)
• Translates any single-ended input signal (LVCMOS, LVTTL, GTL)
to 3.3V LVPECL levels with resistor bias on nCLK or nPCLK
inputs
• Output skew: 20ps (typical)
• Part-to-part skew: 90ps (typical)
• Propagation delay: 885ps (typical), PCLK
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package