1. General description
The 74AVC4T3144 is a 4-bit, dual-supply level translating buffer with 3-state outputs. It features
four data inputs (An and B4), four data outputs (YBn and YA4), and an output enable input (OE).
The device is configured to translate three inputs from VCC(A) to VCC(B) and one input from VCC(B)
to VCC(A). OE, An and YA4 are referenced to VCC(A) and YBn and B4 are referenced to VCC(B). A
HIGH on OE causes the outputs to assume a high-impedance OFF-state.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables outputs, preventing any damaging backflow current through the device when it is powered
down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all outputs are in the highimpedance
OFF-state.
2. Features and benefits
• Wide supply voltage range:
• VCC(A): 0.8 V to 3.6 V
• VCC(B): 0.8 V to 3.6 V
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8-B (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114E Class 3B exceeds 8000 V
• CDM JESD22-C101C exceeds 1000 V
• Maximum data rates:
• 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
• 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
• 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
• 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
• 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
• 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
• Suspend mode
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• IOFF circuitry provides partial Power-down mode operation
• Specified from -40 °C to +85 °C and -40 °C to +125 °C