GENERAL DESCRIPTION

The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 8x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.

FEATURES

• Fully Integrated PLL

• Intelligent Dynamic Clock Switch

• LVPECL Clock Outputs

• LVCMOS Control I/O

• 3.3V Operation

• 32-Lead LQFP Packaging

• 19.44 to 155.52 MHz