72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 2.5V core power supply (VDD)
• 2.5V/1.8V IO supply (VDDQ)
• Fast clock-to-output times
   — 3.0 ns (for 250-MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel®
   Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1484V25, CY7C1485V25 available in JEDEC
   standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free
   165-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option