GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
    - CAS Latency (1, 2 & 3 )
    - Burst Length ( 1, 2, 4, 8 & full page )
    - Burst Type ( Sequential & Interleave )
• All inputs are sampled at the positive going edge of the system clock
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)