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CD54HC4520F Scheda tecnica (PDF) - Texas Instruments

CD54HC4520F Datasheet PDF - Texas Instruments
Il numero della parte CD54HC4520F
Scarica  CD54HC4520F Scarica
Grandezza file   367.32 Kbytes
Page   16 Pages
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments
Spiegazioni elettronici High-Speed CMOS Logic Dual Synchronous Counters

CD54HC4520F Datasheet (PDF)

Go To PDF Page Scarica Scheda tecnica
CD54HC4520F Datasheet PDF - Texas Instruments

Il numero della parte CD54HC4520F
Scarica  CD54HC4520F Click to download

Grandezza file   367.32 Kbytes
Page   16 Pages
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments
Spiegazioni elettronici High-Speed CMOS Logic Dual Synchronous Counters

CD54HC4520F Scheda tecnica (HTML) - Texas Instruments


CD54HC4520F Dettagli del prodotto

Features
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description
The CD74HC4518 is a dual BCD up-counter. The ’HC4520
and CD74HCT4520 are dual binary up-counters. Each
device consists of two independent internally synchronous
4-stage counters. The counter stages are D-type flip-flops
having interchangeable CLOCK and ENABLE lines for
incrementing on either the positive-going or the negativegoing
transition of CLOCK. The counters are cleared by high
levels on the MASTER RESET lines. The counter can be
cascaded in the ripple mode by connecting Q3 to the
ENABLE input of the subsequent counter while the CLOCK
input of the latter is held low.




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