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ADC08D500 Scheda tecnica (PDF) - Texas Instruments

ADC08D500 Datasheet PDF - Texas Instruments
Il numero della parte ADC08D500
Scarica  ADC08D500 Scarica
Grandezza file   990.74 Kbytes
Page   48 Pages
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments
Spiegazioni elettronici ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

ADC08D500 Datasheet (PDF)

Go To PDF Page Scarica Scheda tecnica
ADC08D500 Datasheet PDF - Texas Instruments

Il numero della parte ADC08D500
Scarica  ADC08D500 Click to download

Grandezza file   990.74 Kbytes
Page   48 Pages
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments
Spiegazioni elettronici ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

ADC08D500 Scheda tecnica (HTML) - Texas Instruments


ADC08D500 Dettagli del prodotto

1FEATURES
2• Internal Sample-and-Hold
• Single +1.9V ±0.1V Operation
• Choice of SDR or DDR Output Clocking
• Interleave Mode for 2x Sampling Rate
• Multiple ADC Synchronization Capability
• Ensured No Missing Codes
• Serial Interface for Extended Control
• Fine Adjustment of Input Full-Scale Range and selfOffset
• Duty Cycle Corrected Sample Clock

APPLICATIONS
• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-Top Boxes
• Communications Systems
• Test Instrumentation

KEY SPECIFICATIONS
• Resolution 8 Bits
• Max Conversion Rate 500 MSPS (min)
• Bit Error Rate 10-18 (typ)
• ENOB @ 250 MHz Input 7.5 Bits (typ)
• DNL ±0.15 LSB (typ)
• Power Consumption
– Operating 1.4 W (typ)
– Power Down Mode 3.5 mW (typ)

DESCRIPTION
The ADC08D500 is a dual, low power, high
performance CMOS analog-to-digital converter that
digitizes signals to 8 bits resolution at sampling rates
up to 500 MSPS. Consuming a typical 1.4 Watts at
500 MSPS from a single 1.9 Volt supply, this device
is ensured to have no missing codes over the full operating temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the selfOffset
calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a
high 7.5 ENOB with a 250 MHz input signal and a
500 MHz sample rate while providing a 10-18 B.E.R.
Output formatting is offset binary and the LVDS
digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode
voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds
two LVDS buses and reduces the output data rate on
each bus to half the sampling rate. The two
converters can be interleaved and used as a single 1
GSPS ADC.
The converter typically consumes less than 3.5 mW
in the Power Down Mode and is available in a 128-
lead, thermally enhanced exposed pad HLQFP and
operates over the Industrial (-40°C ≤ TA ≤ +85°C)
temperature range.




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