DESCRIPTION
This device (XL9535/XL9555) is a 24-pin CMOS IC that provides 16-bit of General Purpose parallel
Input/Output (GPIO) expansion for most micro-controller families via the I2C-bus/SMBus interface
[serial clock line (SCL), serial data line (SDA)]. These device is designed for 2.3-V to 5.5-V VCC
operation. The improvements include higher drive capability, 5 V I/O tolerance, lower supply
current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple
solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans,
etc.
These device consists of two 8-bit Configuration (Input or Output selection); Input Port, Output Port
and Polarity Inversion (active-HIGH or active-LOW operation) registers. At power on, the I/Os are
configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or
Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion
register. All registers can be read by the system master.
These device open-drain interrupt (INT) output is activated when any input state differs from its
corresponding Input Port register state and is used to indicate to the system master that an input
state has changed. The system master can reset these device in the event of a timeout or other
improper operation by utilizing the power-on reset feature. The power-on reset sets the registers to
their default values and initializes the I2C/SMBus state machine. Three hardware address pins (A0,
A1 and A2) vary the fixed I2C-bus address and allow up to eight devices to share the same
I
2C-bus/SMBus.

FEATURES
l I
2C-bus to 16-bit GPIO expander
l Operating power supply voltage range of
2.3-V to 5.5-V
l Low standby current consumption
l 5 V tolerant I/O ports
l 400 kHz fast-mode I2C-bus clock
frequency
l Noise filter on SCL/SDA inputs
l Internal power-on reset
l No glitch on power-up
l Polarity Inversion register
l Address by 3 hardware address pins for
use of up to 8 devices
l Open-drain active LOW interrupt output
l 16 I/O pins which default to 16 inputs
l Latch-up testing exceeds 100 mA per JESD
78
l ESD protection exceeds JESD 22
2000 V HBM, 200 V MM and 1000 V CDM