1FEATURES
2• IEEE 1149.1 (JTAG) Compliant and At-Speed
BIST Test Mode.
• Clock Recovery From PLL Lock to Random
Data Patterns.
• Specified Transition Every Data Transfer Cycle
• Chipset (Tx + Rx) Power Consumption < 600
mW (typ) @ 80 MHz
• Single Differential Pair Eliminates Multi-
Channel Skew
• 800 Mbps Serial Bus LVDS Data Rate (At 80
MHz Clock)
• 10-Bit Parallel Interface for 1 Byte Data Plus 2
Control Bits
• Synchronization Mode and LOCK Indicator
• Programmable Edge Trigger on Clock
• High Impedance on Receiver Inputs When
Power is Off
• Bus LVDS Serial Output Rated for 27Ω Load data•
Small 49-Lead NFBGA Package

DESCRIPTION
The SCAN921025 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed
Bus LVDS serial data stream with embedded clock.
The SCAN921226 receives the Bus LVDS serial data
stream and transforms it back into a 10-bit wide
parallel data bus and recovers parallel clock.
Both devices are compliant with IEEE 1149.1
Standard for Boundary Scan Test. IEEE 1149.1
features provide the design or test engineer access
via a standard Test Access Port (TAP) to the
backplane or cable interconnects and the ability to
verify differential signal integrity. The pair of devices
also features an at-speed BIST mode which allows
the interconnects between the Serializer and
Deserializer to be verified at-speed.
The SCAN921025 transmits data over backplanes or
cable. The single differential pair data path makes
PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously
reduce cost. Since one output transmits clock and
data bits serially, it eliminates clock-to-data and data•
to-data skew. The powerdown pin saves power by
reducing supply current when not using either device.
Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the
Deserializer to use the synchronization-to-randomdata
feature. By using the synchronization mode, the
Deserializer will establish lock to a signal within
specified lock times. In addition, the embedded clock
ensures a transition on the bus every 12-bit cycle.
This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921025 output pins into Tri-state to achieve a
high impedance state. The PLL can lock to
frequencies between 30 MHz and 80 MHz.