1 Features
• AEC-Q100 qualified for automotive applications:
– Device temperature grade 1: -40°C to +125°C
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
• Available in wettable flank QFN package
• Low delay, 7.2ns at 5V, 15pF load
• Supports 130MHz at 5V, 15pF load
• Latch-up performance exceeds 250mA
per JESD 17

2 Applications
• Parallel data storage
• Digital bus buffer

3 Description
The SN74AHCT373-Q1 contains eight D-type latches.
All channels share a latch enable (LE) input and
output enable (OE) input.
The input is designed with a reduced threshold circuit
to support up translation when the supply voltage
is larger than the input voltage. Additionally, the 5V
tolerant input pins enable down translation when the
input voltage is larger than the supply voltage. The
output level is always referenced to the supply voltage
(VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS
levels.