Features
 Single issue, 32-bit Power Architecture® Book
E compliant e200z335 CPU core complex
– Includes Variable Length Encoding (VLE)
enhancements for code size reduction
 32-channel Direct Memory Access controller
(DMA)
 Interrupt Controller (INTC) capable of handling
364 selectable-priority interrupt sources: 191
peripheral interrupt sources, 8 software
interrupts and 165 reserved interrupts.
 Frequency-Modulated Phase-Locked Loop
(FMPLL)
 Calibration External Bus Interface (EBI)(a)
 System Integration Unit (SIU)
 Up to 1.5 Mbyte on-chip Flash with Flash
controller
– Fetch Accelerator for single cycle Flash
access @80 MHz
 Up to 94 Kbyte on-chip static RAM (including
up to 32 Kbyte standby RAM)
 Boot Assist Module (BAM)
 32-channel second-generation enhanced Time
Processor Unit (eTPU)
– 32 standard eTPU channels
– Architectural enhancements to improve
code efficiency and added flexibility
 16-channels enhanced Modular Input-Output
System (eMIOS)
 Enhanced Queued Analog-to-Digital Converter
(eQADC)
 Decimation filter (part of eQADC)
 Silicon die temperature sensor
 2 Deserial Serial Peripheral Interface (DSPI)
modules (compatible with Microsecond Bus)
 2 enhanced Serial Communication Interface
(eSCI) modules compatible with LIN
 2 Controller Area Network (FlexCAN) modules
that support CAN 2.0B
 Nexus Port Controller (NPC) per IEEE-ISTO
5001-2003 standard
 IEEE 1149.1 (JTAG) support
 Nexus interface
 On-chip voltage regulator controller that
provides 1.2 V and 3.3 V internal supplies from
a 5 V external source.
 Designed for LQFP144, and LQFP176