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LMK1D2102 Scheda tecnica (PDF) - Texas Instruments

LMK1D2102 Datasheet PDF - Texas Instruments
Il numero della parte LMK1D2102
Scarica  LMK1D2102 Scarica
Grandezza file   1533.51 Kbytes
Page   33 Pages
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments
Spiegazioni elettronici LMK1D210x Low Additive Jitter LVDS Buffer

LMK1D2102 Datasheet (PDF)

Go To PDF Page Scarica Scheda tecnica
LMK1D2102 Datasheet PDF - Texas Instruments

Il numero della parte LMK1D2102
Scarica  LMK1D2102 Click to download

Grandezza file   1533.51 Kbytes
Page   33 Pages
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments
Spiegazioni elettronici LMK1D210x Low Additive Jitter LVDS Buffer

LMK1D2102 Scheda tecnica (HTML) - Texas Instruments


LMK1D2102 Dettagli del prodotto

1 Features
• High-performance LVDS clock buffer family: up to
2 GHz
– Dual 1:2 differential buffer
– Dual 1:4 differential buffer
• Supply voltage: 1.71 V to 3.465 V
• Fail-safe input operation
• Low additive jitter: < max 60 fs RMS in 12-kHz to
20-MHz @ 156.25 MHz
– Very low phase noise floor: -164 dBc/Hz
(typical)
• Very low propagation delay < 575 ps max
• Output skew of 20 ps max
• Universal inputs accept LVDS, LVPECL, LVCMOS,
HCSL and CML signal levels.
• LVDS reference voltage, VAC_REF, available for
capacitive coupled inputs
• Industrial temperature range: –40°C to 105°C
• Packaged in
– LMK1D2102: 3-mm x 3-mm, 16-Pin VQFN
– LMK1D2104: 5-mm x 5-mm, 28-Pin VQFN

2 Applications
• Telecommunications and networking
• Medical imaging
• Test and measurement
• Wireless infrastructure
• Pro audio, video and signage

3 Description
The LMK1D210x clock buffer distributes two clock
inputs (IN0 and IN1) to a total of up to 8 pairs of
differential LVDS clock outputs (OUT0, OUT7) with
minimum skew for clock distribution. Each buffer block
consists of one input and up to 4 LVDS outputs. The
inputs can either be LVDS, LVPECL, HCSL, CML or
LVCMOS.
The LMK1D210x is specifically designed for driving
50-Ω transmission lines. In case of driving the inputs
in single-ended mode, the appropriate bias voltage as
shown in Figure 9-6 must be applied to the unused
negative input pin.
Using the control pin (EN), output banks can either
be enabled or disabled. If this pin is left open, two
buffers with all outputs are enabled, if switched to
a logic "0", both banks with all outputs are disabled
(static logic "0"), if switched to a logic "1", one bank
and its outputs are disabled while another bank with
its outputs are enabled. The part supports a fail-safe
function. The device further incorporates an input
hysteresis which prevents random oscillation of the
outputs in the absence of an input signal.
The device operates in 1.8-V or 2.5-V or 3.3-V
supply environment and is characterized from –40°C
to 105°C (ambient temperature). The LMK1D210x
package variant is shown in the table below:




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