• Jitter below 100fs RMS maximum (10kHz to 20MHz)
• PLL core consists of fractional-feedback Analog
PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
○ Operates from an integrated 60MHz crystal
○ APLL frequency independent of input / crystal frequency
○ Operates as a frequency synthesizer, jitter
attenuator, or Digitally Controlled Oscillator (DCO)
○ DPLL loop filter programmable from 10Hz to 12kHz
○ DCO has tuning granularity of < 1ppb
• Programmable input buffer supports HCSL, LVDS,
or two LVCMOS with no external terminations needed
○ Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS)
○ Reference monitor qualifies/disqualifies input clock