64-MHz, 32-bit RX MCUs, on-chip FPU, 355 Coremark, up to 512-KB flash memory,
up to 36 pins capacitive touch sensing unit, up to 11 comms channels, 12-bit A/D, D/A, RTC,
IEC60730 compliance, 1.6-V to 5.5-V single supply, Encryption functions (optional)

■ 32-bit RXv3 CPU core
 Maximum operating frequency: 64 MHz
Capable of 355 Coremark in operation at 64 MHz
 Enhanced DSP instructions: 32-bit multiply-accumulate instructions,
and 16-bit multiply-subtract instructions are supported.
 On-chip FPU: 32-bit single-precision floating point compliant with
IEEE-754
 On-chip divider that operated at the fastest of two clock cycles
 Fast interrupt
 CISC Harvard architecture with 5-stage pipeline
 Variable-length instructions, ultra-compact code
 On-chip debugging circuit
 Memory protection unit (MPU) supported
■ Low power design and architecture
 Operation from a single 1.6-V to 5.5-V supply
 Four low power consumption modes
 Low power timer (LPT) that operates during the software standby state
 Supply current
High-speed operating mode: 84 μA/MHz
Supply current in software standby mode: 1.01 μA (typ.) (Ta = 25°C)
 Recovery time from software standby mode: 6.3 μs (typ.) (Clock
Source: HOCO 64 MHz, Ta = 25°C)
■ On-chip flash memory for code
 256 K/384 K/512 Kbytes size capacities
 User code is programmable by on-board programming.
 Programmable at 1.6 V
 For instructions and operands
■ On-chip data flash memory
 8 Kbytes (1,000,000 program/erase cycles (typ.))
 BGO (Background Operation)