Description

Information at the D inputs of the HD74HC175 is transferred to the Q and Qoutputs on the positive going edge of the clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Clearing isaccomplished by a negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four Qoutputs to a logic high level.

Features

•  High Speed Operation: tpd(Clock to Q) = 14 ns typ (CL= 50 pF)

•  High Output Current: Fanout of 10 LSTTL Loads

•  Wide Operating Voltage: VCC= 2 to 6 V

•  Low Input Current: 1 µA max

•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)