DESCRIPTION
The IDT82V3385 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications.
The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing.
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less config urable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path.
An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance.
The device provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements.
A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm.
All the read/write registers are accessed through a microprocessor interface. The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial.

FEATURES
HIGHLIGHTS
• The first single PLL chip:
   • Features 0.5 mHz to 560 Hz bandwidth
   • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet
   • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/Option I) jitter generation requirements
   • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
   • Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
  
APPLICATIONS
• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipments
• Synchronous Ethernet equipments
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• IP and ATM core switches and access equipments
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipments
• Any other telecom equipments that need synchronous equipment system timing