GENERAL DESCRIPTION
The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

FEATURES
   11-bit, 250 MSPS output data rate per channel
   Performance with NSR enabled
      SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS
      SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS
   Performance with NSR disabled
      SNR: 66.2 dBFS up to 90 MHz at 250 MSPS
      SFDR: 85 dBc up to 185 MHz at 250 MSPS
   Total power consumption: 706 mW at 200 MSPS
   1.8 V supply voltages
   LVDS (ANSI-644 levels) outputs
   Integer 1-to-8 input clock divider (625 MHz maximum input)
   Internal ADC voltage reference
   Flexible analog input range
      1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
   Differential analog inputs with 400 MHz bandwidth
   95 dB channel isolation/crosstalk
   Serial port control
   Energy saving power-down modes

APPLICATIONS
   Communications
   Diversity radio and smart antenna (MIMO) systems
   Multimode digital receivers (3G)
      WCDMA, LTE, CDMA2000
      WiMAX, TD-SCDMA
   I/Q demodulation systems
   General-purpose software radios