Description
The T7121 HDLC Interface for ISDN (HIFI-64) connects serial communications links carrying HDLC bitsynchronous data frames to 8-bit microcomputer systems. There is an optional transparent mode of operation in which no HDLC processing is performed on user data. The device communicates with the system microprocessor as a memory-mapped peripheral and is controlled by reading and writing 19 internal registers. The chip can be instructed to interrupt the microprocessor when it detects certain events requiring microprocessor attention.

Features
■ Low-cost device for B-channel (64 kbits/s) or D-channel (16 kbits/s) data transport.
■ Optional transparent mode—no HDLC framing is performed.
■ Frame sync (FS) allows a slot-select feature to access an individual time slot in any TDM data stream (e.g., Lucent Technologies Microelectronics Group Concentration Highway Interface [CHI] or subset).
■ Bit-masking option allows effective data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s.
■ Maximum data rate up to 4.096 MHz.
■ Serial data-transfer pins for direct connection to the Lucent ISDN line transceiver T7250C.
■ Supports IOM2, K2, GCI, and SLD interface.
■ Parallel microprocessor interface with either multiplexed or demultiplexed address and data lines for easy interface with any microprocessor.
■ Single interrupt output signal with seven maskable interrupt conditions.
■ Programmable interrupt modes.
■ Memory-mapped read and write registers.
■ TTL/CMOS compatible input/output.
■ 3-state output pins to assist system diagnostics.
■ Low-power 1.25 µm CMOS:
   — 30 mW typical operation at 12 MHz.
   — 5 mW standby mode (typical).
■ HDLC transceiver:
   — Stand-alone HDLC framing operation.
   — 64-byte FIFO in both transmit and receive directions.
   — Supports block-move instruction.
   — Multiple frames allowed in FIFO.
   — Programmable FIFO full- and empty-level interrupt.